There is a logic analyzer method that debugs an actual device by inserting a debug circuit into a debug target circuit during its implementation in order to confirm whether or not the hardware operates normally.
In the logic analyzer method, the debug circuit monitors a temporal change of a signal of a debug target circuit which is specified by a user. Then, the debug circuit stops operation of the debug target circuit when the signal value satisfies a predetermined stop condition, and outputs the signal temporal change recorded in a trace memory to a display device or the like.
See, for example, Japanese Laid-open Patent Publication No. 2003-46393 and M. Walma, “Pipelined Cyclic Redundancy Check (CRC) Calculation”, Proc. of 16th Int'l Conf. on Computer Communications and Networks, pp. 365-370, 2007.
In the meantime, when software is debugged, a program is stopped under various conditions by using a break point. However, when hardware is debugged, it is difficult to stop the hardware at conditions and time points desirable for a user because of hardware constraints, such as the capacity of a trace memory and the number of signal lines that can be used in debugging, and thus it is difficult to debug the hardware efficiently. Thus, a problem is to improve the work efficiency of debugging.